1. Field of the Invention
This invention relates to a voltage generating circuit, for example, a voltage generating circuit capable of outputting multi-level voltages having a plurality of different levels in accordance with input signals, a spatial light modulating element and a display system constituted by using the voltage generating circuit, and a driving method for display system having the spatial light modulating element.
2. Description of the Related Art
In a display system, for example, in a liquid crystal display, an image signal having predetermined luminance can be displayed by controlling the light intensity of each pixel in accordance with image information to be displayed. Therefore, it is necessary to provide, with respect to each pixel, an electrode for controlling a light modulating element constituting the pixel, and control the voltage of the corresponding electrode for changing the light modulation characteristic of each pixel in accordance with image information to be displayed. It is desired to provide a voltage generating circuit which generates a predetermined voltage in accordance with image information to be displayed by each electrode.
In a display which displays general image information such as image signals of television broadcast or image signals displayed on a computer monitor, a display screen is constituted by arraying an extremely large quantity of pixels. To control all the electrodes provided in accordance with these pixels, a voltage generating circuit which enables miniaturization, lower dissipation power and high-speed operation is required.
FIGS. 1A to 1E show exemplary structures of generally used voltage generating circuits. FIG. 1A is a circuit diagram of a load resistance type voltage generating circuit constituted by an nMOS transistor NT and a resistance element RL. As shown in FIG. 1A, an input signal Sin is supplied to the gate of the nMOS transistor NT, and the drain is connected to a power-supply voltage Vcc through the resistance element RL. The source is connected to a common electric potential Vss (or grounded).
Similarly, FIG. 1B is a circuit diagram of a load resistance type voltage generating circuit constituted by a pMOS transistor PT and a resistance element RL. As shown in FIG. 1B, an inversion signal/Sin of an input signal Sin is applied to the gate of the pMOS transistor PT, and the source of the pMOS transistor is connected to a power-supply voltage Vcc. The drain is grounded through a resistance element RL.
In the load resistance type voltage generating circuits shown in FIGS. 1A and 1B, a current flowing through the nMOS transistor NT or the pMOS transistor PT is set in accordance with the level of the input signal Sin or its inversion signal/Sin. Therefore, the level of an output signal Sout outputted from the drain of the nMOS transistor NT or the pMOS transistor PT is set by the input signal Sin or its inversion signal/Sin.
FIG. 1C shows an example of a CMOS type voltage generating circuit constituted by a pMOS transistor PT1 and an nMOS transistor NT1. As shown in FIG. 1C, both of the gates of the pMOS transistor PT1 and the nMOS transistor NT1 are connected to a terminal for an input signal Sin. The source of the pMOS transistor PT1 is connected a power-supply voltage Vcc, and the source of the nMOS transistor NT1 is connected to a common electric potential Vss. In addition, the drains of these two transistors are connected to each other, and the connection point becomes a terminal for an output signal Sout.
In the voltage generating circuit of FIG. 1C, the ON/OFF states of the pMOS transistor PT1 and the nMOS transistor NT1 are controlled in accordance with the input signal Sin, and the level of the output signal Sout is controlled accordingly. For example, when the input signal Sin is at a low level such as the level of the common electric potential Vss or a level proximate thereto, the pMOS transistor PT1 is held in the ON state while the nMOS transistor NT1 is held in the OFF state. Therefore, the output signal Sout is held at the level of the power-supply voltage Vcc. On the contrary, when the input signal Sin is at a high level such as the level of the power-supply voltage Vcc or a level proximate thereto, the pMOS transistor PT1 is held in the OFF state while the nMOS transistor NT1 is held in the ON state. Therefore, the output signal Sout is held at the level of the common electric potential Vss.
Thus, the voltage generating circuit of FIG. 1C supplies the output signal Sout having the inverted logical level of that of the input signal Sin.
FIG. 1D is a circuit diagram of a buffer type voltage generating circuit constituted by a pMOS transistor PT2, an nMOS transistor NT2, and resistance elements RF1, RF2. As shown in FIG. 1D, both of the gates of the pMOS transistor PT2 and the nMOS transistor NT2 are connected to a terminal for an input signal Sin. The source of the pMOS transistor PT2 is connected to a power-supply voltage Vcc, and the source of the nMOS transistor NT2 is connected to a common electric potential Vss. In addition, the resistance elements RF1 and RF2 are connected in series between the drains of the pMOS transistor PT2 and the nMOS transistor NT2, and the connection point of the resistance elements forms a terminal for an output signal Sout.
Similarly to the CMOS type voltage generating circuit of FIG. 1C, the voltage generating circuit of FIG. 1D provides the output signal Sout having an inverted logical level of that of the input signal Sin. In the voltage generating circuit of this example, the resistance elements RF1, RF2 constitute feedback resistance elements, thus compensating temperature characteristics of the MOS transistors PT2, NT2. In general, a drain current of the MOS transistor has a negative temperature characteristic. By providing the resistance element for temperature compensation, the negative temperature characteristic of the drain current can be restrained.
FIG. 1E is a circuit diagram of a DRAM type voltage generating circuit. As shown in FIG. 1E, the voltage generating circuit of this example is constituted by an nMOS transistor NT2 with its source connected to a data line DL and with its gate connected to a control line CL, and a capacitor CS connected between the nMOS transistor NT2 and a common electric potential Vss.
In accordance with a control signal inputted to the control line CL, the ON/OFF state of the transistor NT2 is controlled. When the transistor NT2 is in the ON state, a signal on the data line DL is outputted to the drain side of the transistor NT2, and the capacitor CS is charged accordingly. If a voltage drop of the transistor NT2 can be ignored, the capacitor CS is charged to the same level as an input voltage of the data line DL. In addition, after the transistor NT2 is set in the OFF state by the control signal of the control line CL, the level of an output signal Sout is held.
In order to enhance the driving capability in the case where a load circuit to be driven by the voltage generating circuit has a low impedance, the buffer of FIG. 1D can be provided on the output side of the voltage generating circuits of FIGS. 1A, 1B and 1E.
Meanwhile, the recent semiconductors have been becoming more advanced in features such as increase in operating speed, increase in integration, fine processing, and reduction in voltage. Among these features, the reduction in voltage provides an effect of square with respect to reduction in dissipation power (i.e., dissipation power xe2x88x9dvoltage2). Therefore, the reduction in voltage has been desired increasingly.
For example, since a liquid crystal display has a large number of long distributing electrodes, the electrode capacity is large. Moreover, since a signal of 10 V or more is usually handled, invalid dissipation power occupies a large part of charge/discharge of the stray capacitance. For example, if the driving voltage can be halved to 5 V, the charging/discharging power of the stray capacitance can be reduced to approximately xc2xc of the power at the time of 10-V driving. Therefore, reduction in voltage is an effective measure for reducing dissipation power.
FIG. 2 is a circuit diagram showing an exemplary structure of a liquid crystal display constituted by using the DRAM type voltage generating circuit of FIG. 1E. The liquid crystal display is constituted by a plurality of pixels generally arranged in a matrix form, and each pixel is constituted by a voltage generating circuit for supplying a predetermined driving voltage to a driving electrode and a liquid crystal material held between the driving electrode and an electrode held at a common electric potential. As shown in FIG. 2, the output side of the DRAM type voltage generating circuit (hereinafter referred to as a driving circuit) constituted by the nMOS transistor and the capacitor is connected to the driving electrode. In FIG. 2, the electrode at the common electric potential and the liquid crystal material of each pixel are not shown.
In displaying an image signal, pixel data is generated in accordance with an image signal to be displayed and is inputted to data lines DL1, DL2, . . . , DLm. Since a control signal having a predetermined level is sequentially applied to scanning lines SL1, SL2, . . . , SLn in accordance with the input timing of the pixel data to the data lines DL1, DL2, . . . , DLm, the nMOS transistor at each pixel is set in the ON state and the capacitor is charged in accordance with the pixel data. Then, since the voltage held by the capacitor of each pixel is applied to driving electrodes PAD11, . . . , PADm1, PAD 12, . . . , PADm2, PAD1n, . . . , PADmn, the light modulation characteristic such as the refractive index or reflectivity of the liquid crystal material of each pixel is controlled in accordance with the driving voltage applied to each driving electrode. Thus, the image signal corresponding to the pixel data is displayed.
In the display system thus constituted, since the DRAM type voltage generating circuit of FIG. 1E is used, the data lines DL1, DL2, . . . , DLm need to be driven with a large amplitude having an electric potential equal to or higher than that of the output signal Sout. In addition, since the nMOS transistor is generally used, the output signal is driven only with an amplitude of Vpp-Vth-dVth even when the scanning lines SL1, SL2, . . . , SLn are driven at a certain electric potential Vpp. In this case, Vth represents a threshold voltage of the nMOS transistor, and dvth represents a rise of effective Vth due to a board bias effect.
As a measure for overcoming this, it can be considered to employ the voltage generating circuit using a resistance load, as shown in FIGS. 1A and 1B. However, if the transistor is in the ON state in the case where the resistance load is used, a current continues to flow through the resistance load. Therefore, heating of the resistance load and dissipation power become problematical particularly in a VLSI (very large scale integrated circuit). Also, in a multi-level voltage generating circuit capable of outputting a plurality of different voltage levels, unevenness of the resistance load causes a problem.
On the other hand, in the case of the CMOS structure in which the nMOS transistor and the pMOS transistor coexist as shown in FIGS.1C and 1D, a through current generated by setting both the nMOS transistor and the pMOS transistor in the ON state and dissipation power due to the through current cause problems. To prevent such problems, an input signal having an amplitude equal to an output logical amplitude is generally required. Therefore, when a large amplitude output is necessary, increase in pressure resistance of the circuit structure and a level shift circuit are required. However, in this case, too, the through current at the moment of switching of the circuit state is still a problem.
To minimize the through current, an output transition period must be reduced and the rise of the input signal must be made sufficiently quick. That is, a signal having a high amplitude and a high through rate is required.
If the voltage is raised, an insulating region is required between the nMOS transistor and the pMOS transistor. Since problems of latch up of the transistors and the like are likely occur when the voltage becomes higher, the transistors must be separated sufficiently from each other, thus causing such inconvenience that it is difficult to constitute the CMOS circuit in a narrow region.
In view of the foregoing status of the art, it is an object of the present invention to provide a voltage generating circuit which is capable of controlling an output signal of a large amplitude by a small-amplitude signal without using load resistance, and which enables realization of miniaturization, reduction in voltage, and reduction in dissipation power.
According to the present invention, there is provided a voltage generating circuit which operates in accordance with an input signal and outputs a signal having at least two levels to an output node, the voltage generating circuit including: a capacitor connected between the output node and a common electric potential; first level setting means for charging the capacitor with a predetermined voltage in accordance with a first input signal, thus setting the electric potential of the output node at a first level; and second level setting means for controlling discharge operation of the capacitor in accordance with a second input signal, thus setting the electric potential of the output node at a second level different from the first level.
According to the present invention, there is also provided a spatial light modulating element having a plurality of pixels and adapted for modulating a light by each pixel in accordance with pixel data based on an image signal to be displayed, the spatial light modulating element including, for each pixel: a voltage generating circuit having first level setting means for setting the electric potential of an output node at a first level in accordance with a first input signal, level holding means for holding the level of the output node, and second level setting means for setting the electric potential of the output node at a second level different from the first level in accordance with a second input signal; and control means for outputting the second input signal in accordance with the pixel data.
According to the present invention, there is also provided a display system including: a light source for radiating a light; and a spatial light modulating element having a plurality of pixels and adapted for modulating a light radiated from the light source by each pixel in accordance with pixel data based on an image signal to be displayed. The spatial light modulating element includes, for each pixel: a voltage generating circuit having first level setting means for setting the electric potential of an output node at a first level in accordance with a first input signal, level holding means for holding the level of the output node, and second level setting means for setting the electric potential of the output node at a second level different from the first level in accordance with a second input signal; and control means for outputting the second input signal in accordance with the pixel data.
According to the present invention, there is further provided a driving method for display system for driving each pixel of a spatial light modulating element having a plurality of pixels and adapted for modulating a light by each pixel in accordance with pixel data based on an image signal to be displayed, the method including: a first step of charging a capacitor provided between an output node connected to each pixel and a common electric potential in accordance with a first input signal, thus setting the electric potential of the output node at a first level; and a second step of holding the electric potential of the output node at the first level or setting the electric potential of the output node at a second level different from the first level, in accordance with a second input signal corresponding to the pixel data.